1. Field of the Invention
This invention relates to integrated circuits and more specifically to a high voltage charge pump circuit including transistors formed by a low voltage CMOS semiconductor fabrication process.
2. Description of the Prior Art
It is well known in the field of integrated circuits to fabricate field effect transistors capable of operating at a high voltage. Other field effect transistors which are capable of operating at only a low voltage have the advantage of a higher capacitance and current carrying capability per unit area. Typically, such low voltage transistors are also advantageously considerably smaller in terms of surface area (of higher density) and also involve shallower diffusions than do the high voltage transistors; they are thus easier and less expensive to fabricate. Most digital logic semiconductor circuits use such low voltage (i.e., 2 to 5 volts source-to-gate potential) field effect transistors. In contrast, the high voltage field effect transistors typically require thicker gate oxide, deeper diffusions, and greater surface area in order to withstand the higher voltages (typically exceeding 5 volts source-to-gate potential). The processes to fabricate respectively low voltage and high voltage field effect transistors thus differ considerably, and in the prior art such high and low voltage transistors cannot be fabricated using the same series of process steps.
This becomes a significant limitation when one wants to combine in a single integrated circuit both a high voltage circuit and a low voltage circuit. In that case, it is known to provide a high voltage/low voltage interface as described in the publication "5 V-to-75 V CMOS Output Interface Circuits", Declercq et al., 1993 IEEE International Solid State Circuits Conference, p. 162-163. This publication describes combining low cost, low voltage standard CMOS logic with high voltage CMOS output buffers on the same chip, using a standard unmodified low voltage CMOS processing technology and using level shift techniques to meet the constraints on the gate control signal voltages. Thus the gate-to-source voltage swing of the output devices (which are the high voltage transistors) are within the safe operating limits of the low voltage transistors.
However, it has been found that this solution has several drawbacks. One is that the N channel transistors, typically formed in a P well in the semiconductor substrate, are not effectively isolated electrically from the substrate. Also, problematically for high voltage P channel transistors, there is punch through to the substrate. This is because the N well is relatively shallow beneath the P-field drain region in accordance with the low voltage fabrication technique. This limits the voltage that the P channel transistors can withstand (i.e., to below 30 V).
Therefore, there is a need to combine high density low voltage standard CMOS logic transistors with CMOS transistors operating at high voltage on the same chip and fabricated using a low voltage CMOS technology, without the drawbacks of the technique of the above-referenced publication.